View ICS9248-169_278172.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9248-169
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 440BX/VIA Apollo 133/694X style chipset. Output Features: * 2 - CPUs @2.5V, up to 166MHz. * 1 - IOAPIC @ 2.5V * 13 - SDRAM @ 3.3V * 6 - PCI @3.3V, * 1 - 48MHz, @3.3V fixed. * 1 - 24MHz @ 3.3V * 2 - REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support power management: PCI, CPU stop and Mode * Spread spectrum for EMI control ( 0.50%). * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: <500ps * PCI - PCI: <500ps * CPU(early)-PCI: Typ=1.0ns
Pin Configuration
VDDREF *PCI_STOP/REF0 GND X1 X2 VDDPCI *MODE/PCICLK_F **FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDA BUFFER IN GND SDRAM11 SDRAM10 VDDSDR SDRAM9 SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL IOAPIC REF1/FS2* GND CPUCLK_F CPUCLK1 VDDL CLK_STOP#* SDRAM_F GND SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 VDD48 48MHz/FS0* 24MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND
Block Diagram
PLL2 /2 X1 X2 BUFFER IN XTAL OSC 48MHz 24MHz IOAPIC REF(1:0) CPUCLK_F PLL1 Spread Spectrum FS(3:0) MODE
4
STOP
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 80.00 75.00 83.31 66.82 103.00 112.01 68.01 100.23 120.00 114.99 109.99 105.00 140.00 150.00 124.00 133.33 PCICLK (MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.33
STOP
2
CPUCLK 1
LATCH
STOP
12
SDRAM (11:0) SDRAM_F
4
POR
CLK_STOP# PCI_STOP# SDATA SCLK Control Logic Config. Reg.
PCI CLOCK DIVDER
STOP
5
PCICLK (4:0) PCICLKF
9248-169 Rev A- 6/05/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-169
ICS9248-169
Pin Descriptions
PIN NUMBER 1, 6, 14, 19, 27, 30, 36 2 3,9,16,22, 33,39,45 4 5 P I N NA M E VDD REF0 PCI_STOP#1 GND X1 X2 PCICLK_F 7 MODE1, 2 FS3 8 13, 12, 11, 10 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 23 24 25 26 40 41 42, 48 43 44 46 47 PCICLK0 PCICLK (4:1) BUFFER IN SDRAM (11:0) SDATA SCLK 24MHz FS1
1, 2
TYPE PWR OUT IN PWR IN OUT OUT IN IN OUT OUT IN OUT I/O IN OUT IN OUT IN OUT IN PWR OUT OUT OUT IN OUT 3.3V Power supply
DESCRIPTION
14.318 Mhz reference clock. Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Free running PCI clock not affected by PCI_STOP# for power management. Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Syncheronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant 24MHz output clock Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK1, IOAPIC & SDRAM (0:11) at logic "0" level when driven low. Supply for CPU, IOAPIC clocks, either 2.5V or 3.3V nominal CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Free running CPU clock. Not affected by the CPU_STOP# 14.318 MHz reference clock. Frequency select pin. Latched Input IOAPIC clock output. 14.318 MHz Powered by VDDL1.
48MHz FS01, 2 SDRAM_F CLK_STOP# VDDL CPUCLK1 CPUCLK_F REF1 FS21, 2 IOAPIC
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-169
General Description
The ICS9248-169 is a single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-169 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDREF = REF (1:0), X1, X2 VDDPCI = PCICLK_F, PCICLK(4:0) VDDA = Supply for PLL core VDD48 = 24MHz, 48MHz VDDL = CPUCLK, CPUCLK_F, IOAPIC VDDSDR = SDRAM
Mode Pin - Power Management Input Control
MODE, Pin 7 (Latched Input) 0 1 Pin 2 PCI_STOP# (Input) REF0 (Output)
Third party brands and names are the property of their respective owners.
3
ICS9248-169
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
Third party brands and names are the property of their respective owners.
4
ICS9248-169
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2, Bit 7:4
Bit 3 Bit 1 Bit 0
Description CPUCLK PCICLK Bit (2, 7, 6, 5, 4) (MHz) (MHz) 0 0 0 0 0 80.00 40.00 0 0 0 0 1 75.00 37.50 0 0 0 1 0 83.31 41.65 0 0 0 1 1 66.82 33.41 0 0 1 0 0 103.00 34.33 0 0 1 0 1 112.01 37.34 0 0 1 1 0 68.01 34.01 0 0 1 1 1 100.23 33.41 0 1 0 0 0 120.00 40.00 0 1 0 0 1 114.99 38.33 0 1 0 1 0 109.99 36.66 0 1 0 1 1 105.00 35.00 0 1 1 0 0 140.00 35.00 0 1 1 0 1 150.00 37.50 0 1 1 1 0 124.00 31.00 0 1 1 1 1 133.33 33.33 1 0 0 0 0 135.00 33.75 1 0 0 0 1 129.99 32.50 1 0 0 1 0 126.00 31.50 1 0 0 1 1 118.00 39.33 1 0 1 0 0 115.98 38.66 1 0 1 0 1 95.00 31.67 1 0 1 1 0 90.00 30.00 1 0 1 1 1 85.01 28.34 1 1 0 0 0 166.00 41.50 1 1 0 0 1 160.01 40.00 1 1 0 1 0 154.99 38.75 1 1 0 1 1 147.95 36.99 1 1 1 0 0 145.98 36.50 1 1 1 0 1 143.98 35.99 1 1 1 1 0 141.99 35.50 1 1 1 1 1 138.01 34.50 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0.50% Center Spread 0 - Running 1- Tristate all outputs
PWD
00101 Note1
0 1 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
5
ICS9248-169
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
40 43 44
PWD
X 1 1 1 1 1 1 1
DESCRIPTION
Latched FS2# (Reserved) (Reserved) (Reserved) SDRAM_F (Reserved) CPUCLK1 CPUCLK_F
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
7 13 12 11 10 8
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) PCICLK_F (Reserved) PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
26 25 21,20, 18,17 32,31, 29,28 38,37, 35,34
PWD
1 X 1 1 1 1 1 1
DESCRIPTION
(Reserved) Latched FS0# 48MHz 24 MHz (Reserved) SDRAM (8:11) SDRAM (4:7) SDRAM (0:3)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
1 1 1 1 X 1 X 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved)
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
PIN# PWD
47 46 2 1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) IOAPIC (Reserved) (Reserved) REF1 REF0
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: Don't write into this register, writing into this register can cause malfunction
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
6
ICS9248-169
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-169. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) IOAPIC
SDRAM CPUCLK
CPUCLK _F SDRAM_F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-169. 3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low. 4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-169 CLK_STOP# signal. SDRAM's are controlled as shown. 5. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
7
ICS9248-169
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-169. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-169 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-169 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248-169. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
8
ICS9248-169
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248169 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
9
ICS9248-169
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD =VDDL= 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN=VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors IDD3.3OP66 CL = 0 pF; Select @ 66.8 MHz Operating Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100 MHz Input frequency Fi VDD = 3.3 V Input Capacitance1 Clk Stabilization1
1
MIN 2 VSS-0.3 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 180 16 5 45 3 mA MHz pF pF ms
12 27
94 130 14.318
CIN CINX TSTAB
Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq.
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/- 5%, VDDL= 2.5 V +/-5% (unless otherwise stated) SYMBOL CONDITIONS MIN PARAMETER IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz Operating Supply Current IDD2.5OP100 CL = 0 pF; Select @ 100 MHz Skew1 VT = 1.5V; VTL = 1.25V 0.5 tCPU-PCI
1
TYP
1.12
MAX 72 100 1.5
UNITS mA ns
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
ICS9248-169
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%, VDDL=2.5V +/- 5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -8 mA 2 Output High Voltage VOH2B IOL = 12 mA Output Low Voltage VOL2B IOH2B VOH = 1.7 V Output High Current IOL2B VOL = 0.7 V 19 Output Low Current Rise Time1 Fall Time
1 1
TYP 2.4 0.17 -58 46 1.3 1.0
MAX UNITS V 0.4 V -16 mA mA 1.6 1.6 55 175 250 ns ns % ps ps
tr2B tf2B dt2B tsk2B tjcyc-cyc2B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V 45
Duty Cycle 1 Skew 1 Jitter, Cycle-to-cycle
1
47.5 41 216
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%, VDDL = 2.5V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH1 IOH = -11 mA 2.4 IOL = 9.4 mA Output Low Voltage VOL1 IOH1 VOH = 2.0 V Output High Current IOL1 VOL = 0.8 V 41 Output Low Current Rise Time1 Fall Time
1 1 1
TYP 3.15 0.13 -97 69 1.66 1.52
MAX UNITS V 0.4 V -40 mA mA 2.0 2.0 55 500 500 ns ns % ps ps
tr1 tf1 dt1 tsk1 tjabs1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V -500 45
Duty Cycle
49.7 254 180
Skew Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9248-169
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3V +/-5%, VDDL = 2.5V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH3 IOH = -28 mA 2.4 IOL = 20 mA Output Low Voltage VOL3 IOH3 VOH = 2.0 V Output High Current IOL3 VOL = 0.8 V 41 Output Low Current Rise Time Fall Time
1
TYP 3.0 0.18 -110 86 1.13 1.11
MAX UNITS V 0.4 V -40 mA mA 2 2 55 500 5 ns ns % ps ns
tr3 tf3 dt3 tsk3 Tprop
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 45
1 1
Duty Cycle 1 Skew 1 Propagation Delay
(Buffer In to Output) 1
53.1 215 3.26
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD=3.3V +/- 5%, VDDL=2.5V +/- 5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -8 mA 2 Output High Voltage VOH4B IOL = 12 mA Output Low Voltage VOL4B IOH4B VOH = 1.7 V Output High Current IOL4B VOL = 0.7 V 19 Output Low Current Rise Time Fall Time
1
TYP 2.4 0.17 -58 46 1.14 1.07
MAX UNITS V 0.4 V -16 mA mA 2 2 55 1 ns ns % ns
tr4B tf4B dt4B tjabs4B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V 45 -1
1 1
Duty Cycle 1 Jitter, Absolute
1
52.7 0.27
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9248-169
Electrical Characteristics - REF, 48MHz, 24MHz
TA = 0 - 70C; VDD = 3.3V +/-5%, VDDL = 2.5V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -12 mA 2.4 Output High Voltage VOH5 IOL = 10 mA Output Low Voltage VOL5 IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V 16 Output Low Current Rise Time1 Fall Time
1 1
TYP 3.03 0.23 -50 40 1.26 1.57
MAX UNITS V 0.4 V -22 mA mA 4.0 4.0 55 1 ns ns % ns
tr5 tf5 dt5 tjabs5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V 45 -1
Duty Cycle Jitter, Absolute1
1
53.3 0.25
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS9248-169
N
c
L
SYMBOL
INDEX AREA E1 E
12 D h x 45
a
A A1
-Ce
b SEATING PLANE .10 (.004) C
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
N 48
D (inch) MIN .620 MAX .630
300 mil SSOP Package
Reference Doc.: JEDEC Publication 95, MO-118 10-0034
Ordering Information
ICS9248yF-169-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
14
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

▲Up To Search▲

Price & Availability of ICS9248-169

	To Download ICS9248-169 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .